This invention relates to a process for manufacturing integrated circuits such as complementary metal oxide semiconductor (CMOS) circuits including P-channel field effect transistors (PMOS FETs) and N-channel field effect transistors (NMOS FETs) and resulting products. In the production of integrated circuits on semiconductor substrates, the threshold voltage V.sub.T is set by a threshold adjust implantation of a doped material into the FET's channels. The prior art threshold adjust implantation is described in FIG. 1. FIG. 1 shows p-well 2 and n-well 4 formed on a semiconductor substrate, field oxide regions 6, 8 and 10, and thin gate oxide layers 12 and 14 covering the channels.
In the threshold adjust implantation the voltage threshold V.sub.T of the FET being created is determined by the magnitude of the implantation in the regions 5 and 7 which will be the channels for the FETs.
If no threshold adjust implantation is done before the creation of the PMOS and NMOS FETs, the FETs' threshold voltage would be their native threshold voltage. In the prior art threshold adjust implantation for a 1.2 micron process, a boron ion implant dose of 9.5.times.10.sup.11 Boron ions per cm.sup.2 is typically done to both regions A and region B.
Due to the threshold adjust implantation, the PMOS FET with the channel in region B will have its threshold voltage raised from the PMOS native threshold voltage to the PMOS normal threshold voltage. At the same time, the NMOS FET with its channel in region A will have its threshold voltage raised from the NMOS native threshold voltage to the NMOS normal threshold voltage. In this manner, the PMOS and NMOS FETs with normal threshold voltages are created.
The prior art also includes the use of zero threshold voltage NMOS FETs. These zero threshold voltage NMOS FETs are merely NMOS FETs whose threshold voltage is the native threshold voltage for NMOS FETs. For NMOS FETs, the zero threshold voltage is the native threshold voltage.
The ranges of the normal and native threshold voltages for PMOS and NMOS FETs are discussed below in the detailed description section.